Projects

Projects · GitHub · AI · VLSI · RF · MLOps

Projects

A curated portfolio of hands-on projects across hackathons, computer science, machine learning, MLOps, web development, VLSI design, digital verification, RF signal classification, and hardware-aware computing.

Hackathon Projects Computer Science Machine Learning VLSI and ECE GitHub Portfolio

● Deep Q-Learning

● Worker Safety IoT

● MLOps CI/CD

● Local RAG

● RAPIDS ML

● RTL-to-GDSII

● UVM Verification

● RF Signal Classification

● Deep Q-Learning

● Worker Safety IoT

● MLOps CI/CD

● Local RAG

● RAPIDS ML

● RTL-to-GDSII

● UVM Verification

● RF Signal Classification

Hackathon AI, IoT, analytics, and application projects

CS MLOps, APIs, RAG, CI/CD, and cloud projects

ECE VLSI, Verilog, UVM, TCL, and RF systems

GitHub Open project repositories and code artifacts

🧠

AI and Machine Learning

Projects include deep reinforcement learning, RAPIDS GPU acceleration, MLOps pipelines, Hugging Face deployment, and local RAG workflows.

⚙️

VLSI and Digital Systems

Hands-on ECE projects cover RTL-to-GDSII flows, OpenLANE, SKY130, RISC-V, UVM verification, TCL automation, and Verilog design.

📡

RF and Edge Systems

Projects include RF signal classification, protocol simulation, embedded interfaces, and practical hardware-aware workflows.

📂 Project Categories

Use the tabs below to view projects by category. Each card links directly to the corresponding GitHub repository.

🚀

Lunar Lander using DQN

Deep Q-Learning based game simulation using OpenAI Gym for dynamic control.

DQN Reinforcement Learning OpenAI Gym

View GitHub

🦺

Worker Safety System

IoT-based smart safety monitoring system for industrial workers with instant alerting.

IoT Safety Real-Time Alerts

View GitHub

🏢

Data Centers

Smart data center analytics with optimized power usage and real-time monitoring dashboards.

Analytics Power Optimization Monitoring

View GitHub

🦅

Falcon Application

Personal assistant app.

Application Assistant Software

View GitHub

🖥️

NVIDIA GPU Setup

Instructions to configure NVIDIA drivers, CUDA, cuDNN for DL workloads.

NVIDIA CUDA Deep Learning

View GitHub

🧪

ML Unit Testing

Framework for verifying ML models using unit and integration test cases.

Testing ML Systems Unit Tests

View GitHub

🌐

MEAN Stack App

Full-stack web app using MongoDB, Express, Angular, and Node.js.

MongoDB Express Angular Node.js

View GitHub

☁️

Serverless DL

Running ML models with AWS Lambda functions and API Gateway integration.

AWS Lambda API Gateway Serverless

View GitHub

🤗

HuggingFace CI/CD

End-to-end NLP deployment using HuggingFace transformers with GitHub Actions.

HuggingFace Transformers GitHub Actions

View GitHub

⚡

FastAPI Swagger

REST APIs using FastAPI framework with auto-generated Swagger documentation.

FastAPI Swagger REST API

View GitHub

🚄

RAPIDS ML

GPU-accelerated ML using NVIDIA RAPIDS for large-scale data processing.

RAPIDS GPU ML NVIDIA

View GitHub

🔁

ML Pipeline (DVC)

Building reproducible ML pipelines using Data Version Control.

DVC ML Pipeline Reproducibility

View GitHub

📚

RAG (Local)

Retrieval Augmented Generation pipeline on local knowledge base.

RAG LLM Local AI

View GitHub

🧩

MLOps CI/CD

CI/CD pipeline for ML models using Docker, GitHub Actions, and DVC.

MLOps Docker CI/CD

View GitHub

🧱

PD Flow (Cadence)

RTL to GDSII implementation using Cadence Innovus tools and custom scripts.

Cadence RTL-to-GDSII Physical Design

View GitHub

🔌

SPI & UART

Protocol design and simulation in Verilog for SPI and UART interfaces.

SPI UART Verilog

View GitHub

✅

UVM ALU Testbench

UVM-based testbench for verifying an Arithmetic Logic Unit (ALU).

UVM ALU Verification

View GitHub

➕

SV Testbench - Half Adder

SystemVerilog-based modular test environment for Half Adder validation.

SystemVerilog Half Adder Testbench

View GitHub

📜

TCL Automation

Automated VLSI flow scripting using advanced TCL techniques.

TCL Automation VLSI Flow

View GitHub

🛤️

OpenLANE EDA

ASIC flow using the open-source OpenLANE and Sky130 PDK.

OpenLANE Sky130 ASIC Flow

View GitHub

🧮

RISC-V ISA

RISC-V Instruction Set Architecture design and testing in Verilog.

RISC-V ISA Verilog

View GitHub

🔷

SKY130 RTL Design

RTL design and synthesis using SKY130 technology nodes.

RTL SKY130 Synthesis

View GitHub

🧾

Advanced TCL

Deep dive into TCL scripting with conditionals and design checks.

TCL Scripting Design Checks

View GitHub

📡

RF Signal Classification

Modulation classification using CAF, STFT, and custom ML models.

RF CAF STFT ML

View GitHub

Select the Hackathon, Computer Science, or Electrical & Computer Engineering tabs above for organized project views.

Deep Q-Learning IoT Safety Data Center Analytics NVIDIA CUDA Machine Learning Testing MEAN Stack Serverless ML HuggingFace FastAPI RAPIDS ML DVC Local RAG MLOps Cadence Innovus SPI/UART UVM SystemVerilog TCL Automation OpenLANE RISC-V SKY130 RF Signal Classification